1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of controlling metal etch processes, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Typically, integrated circuit devices are comprised of hundreds or millions of transistors formed above a semiconducting substrate. By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnects, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate 11.
The structure and composition of such conductive interconnects has become very important in modern integrated circuit devices. For example, given the drive for integrated circuit devices with greater operating speeds, circuit designers take great care in designing such conductive interconnects to insure that electrical signals may propagate as quickly as possible within an integrated circuit device. In particular, it is important that the electrical resistance of the conductive interconnects is as low as possible. As a result, conductive interconnects are typically comprised of a metal, such as aluminum, titanium, copper, etc., due to the relatively low resistance of these materials. More particularly, copper has become increasingly popular as an interconnect material due to its very attractive electrical characteristics.
In addition to the material selected for the conductive interconnects, it is important that the physical size of the interconnect structure not be inadvertently reduced during fabrication because such reductions may lead to an undesirable increase in the resistance of the conductive interconnects. Unfortunately, such reductions do occur in semiconductor fabrication, and they can be very difficult to detect, as will be discussed in connection with FIGS. 1B-1C. FIG. 1B is a cross-sectional side view of an illustrative conductive interconnect, i.e., a conductive line 17, formed in a layer of insulating material 19, e.g., silicon dioxide. Also depicted in FIG. 1B are two bottom barrier metal layers 21 and 23, a top barrier layer 25, and a cap layer 27. As will be recognized by those skilled in the art, the structure depicted in FIG. 1B is illustrative only of a portion of a single level of multiple levels of conductive interconnects within a typical integrated circuit device. FIG. 1C is a top view of the structure depicted in FIG. 1B.
As can be seen in FIG. 1B, the conductive line 17 exhibits severe undercutting, as indicated by arrows 31, relatively to an ideal, rectangular shape for the conductive line 17, as indicated by dashed lines 33. Such undercutting is primarily due to the problems associated with etching metals, such as aluminum. Typically, a chlorine-based plasma etch process may be performed to etch aluminum conductive interconnects. However, when etching metals, such as aluminum, such an etching process tends to be somewhat isotropic in nature, thereby producing the undercutting 31 of the conductive interconnect 17. Efforts are made to introduce a passivant during the etching process used to form the conductive interconnect to reduce the undercutting of the conductive interconnect, but such efforts do not completely reduce the undercutting of the conductive interconnect.
Additionally, such undercutting, and the extent of such undercutting, may be difficult to detect with existing metrology tools and methods. In etching the cap layer 27 and the other barrier metal layers, it is relatively easy to achieve a very anisotropic profile of those layers due to the materials used for such layers. These various etching processes result in the structure depicted in FIG. 1B. Unfortunately, commonly employed metrology tools and techniques may not be able to adequately detect the existence or extent of undercutting of the conductive interconnect 17 in such structures. For example, a scanning electron microscope (SEM) may be employed after the conductive interconnect 17 is formed to obtain information about the physical size, i.e., the width, of the conductive interconnect 17. The SEM may be used to take a xe2x80x9ctop-downxe2x80x9d look at the conductive interconnect 17, as indicated by the arrows 35. However, due to the close proximity of the conductive interconnects 17 within a given layer, the existence of the cap layer 27 and the upper barrier layer 25, and the inherent nature of the SEM, the data obtained by the SEM does not reveal the true or entire profile of the conductive interconnect 17. Thus, the profile of the conductive interconnect 17 cannot readily be examined using an SEM.
Typically, one or more production or test wafers that are representative of one or more lots of wafers are eventually cross-sectioned and analyzed to detect the existence of undercutting problems with the conductive interconnects. However, it takes days or weeks to generate results from such destructive testing techniques. During this time, additional conductive interconnects may be being manufactured on additional wafers with undesirable undercutting characteristics, thereby tending to increase the resistance of such conductive interconnects. Moreover, the results of such destructive testing techniques are not provided in sufficient time to provide meaningful and relatively rapid feedback to allow more precise control of the processing parameters used to form the conductive interconnects 17.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a method of controlling metal etch processes, and a system for accomplishing same. In one illustrative embodiment, the method comprises providing a library of optical characteristic traces, each of which correspond to a grating structure comprised of a plurality of conductive interconnects having a known profile, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of conductive interconnects having an unknown profile, and illuminating the grating structure formed above the substrate. The method further comprises measuring light reflected off of the grating structure to generate an optical characteristic trace for the formed grating structure and determining a profile of the conductive interconnects comprising the formed grating structure by correlating the generated optical characteristic trace to an optical characteristic trace from the library. In a further embodiment, the method comprises modifying at least one parameter of at least one etching process used to form conductive interconnects on a subsequently processed substrate based upon the determined profile of the conductive interconnects comprising the formed grating structure.
In another aspect, the present invention is directed to a method whereby a generated trace of a grating structure comprised of a plurality of conductive interconnects having an unknown profile is compared to a target trace established for a grating structure comprised of conductive interconnects having an acceptable profile. In one illustrative embodiment, the method comprises providing a library comprised of at least one optical characteristic trace, one of which is a target trace that corresponds to a grating structure comprised of a plurality of conductive interconnects having a known target profile, and providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of conductive interconnects having an unknown profile. The method further comprises illuminating the grating structure formed above the substrate, measuring light reflected off of the grating structure to generate an optical characteristic trace for the formed grating structure, and comparing the generated optical characteristic trace to the target trace. In a further embodiment, the method further comprises determining, based upon the comparison of the generated optical characteristic trace and the target trace, at least one parameter of at least one etching process used to form conductive interconnects on a subsequently processed substrate.